Interposer to couple a microelectronic device package to a circuit board

ABSTRACT

An interposer to couple a microelectronic device package to a motherboard is formed from a PCB substrate. Multiple via holes are drilled through a copper-clad PCB substrate and then coated inside with copper. The copper surface coating is etched to form multiple traces In one embodiment, the substrate is cut through each row of via holes and between each row of via holes to produce multiple individual beam-and-trace interposers. Two or more such interposers may be affixed together to form a beam-and-trace interposer array. Alternatively, the substrate is not cut into strips, and each via hole is filled completely with a conductive material to form an array of solid conductive columns through the substrate.

[0001] This is a divisional of U.S. patent application No. 10/080,438,filed on Feb. 21, 2002.

FIELD OF THE INVENTION

[0002] The present invention pertains to the fabrication and assembly ofmicroelectronic devices and related components. More particularly, thepresent invention relates to an interposer to couple a microelectronicdevice package to a circuit board.

BACKGROUND OF THE INVENTION

[0003] In microelectronic device manufacturing, a microelectroniccircuit chip, or “die”, is commonly mounted to a “package” before it isintegrated into a larger system. The package serves to protect the dieand may provide a standardized interface between the die and the systemin which it will be used. The package with the integrated die issubsequently mounted to a printed circuit board (PCB), such as amotherboard in a computer system.

[0004] One common technology for connecting these components together isthe ball grid array (BGA), an array of round solder balls that form theinput/output (I/O) terminals between the components. FIG. 1 shows anexample of the current state of the art for attaching BGA components toPCBs. A semiconductor die 1 is mounted to a package 2 by solder balls 4in a first BGA. The package 2 is coupled to a PCB substrate 3 (e.g., amotherboard) by solder balls 5 in a second BGA, which may be of adifferent size and/or composition than solder balls 4 which couple thedie 1 to the package 2.

[0005] With each device generation, the number of inputs and outputsrequired in microelectronic devices tends to increase. This trendincreases the I/O density requirements for ball grid arrays (BGAs). Thusfar, the increase in I/O density requirements has been handled mainly byreducing the solder ball pitch in the BGA. Solder ball pitch is theshortest distance of one ball to the next ball. A reduction in pitch ofa BGA requires scaling down the size the solder balls to beproportionally smaller in diameter. However, smaller diameter solderballs produce a smaller standoff height between the package and the PCBand reduce solder joint strength. This reduction in solder ball strengthcan cause solder joint fatigue during thermal cycling and result inelectrically open solder joints.

[0006] Under-fill epoxy can be used to improve mechanical solder jointstrength and is sometimes used to improve mechanical bonding of thepackage to the PCB. The under-fill process is expensive, however, and isnot conducive to current high volume surface mount technology (SMT) formotherboard manufacturers. The epoxy under-fill process also isproblematic with larger BGAs, where under-fill cannot reliability fillunder the package completely. Furthermore, the epoxy under-fill processmakes it difficult if not impossible to rework faulty components.

[0007] There is a need, therefore, to increase I/O density formicroelectronic devices, without increasing BGA package size or reducingsolder joint reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements and in which:

[0009]FIG. 1 shows an assembly including a die mounted to a package,which is mounted to a PCB using conventional solder balls;

[0010]FIG. 2 illustrates a PCB substrate with an array of via holesdrilled in it;

[0011]FIG. 3A illustrates the PCB substrate of FIG. 2 with the additionof copper traces;

[0012]FIG. 3B illustrates the locations of grooves carved in the PCBsubstrate in making a beam-and-trace interposer;

[0013]FIG. 3C illustrates the locations where the PCB substrate is cutin making a beam-and-trace interposer;

[0014]FIG. 3D illustrates the locations of grooves carved in the PCBsubstrate in making a conductive column interposer

[0015]FIG. 4 illustrates a top or bottom view of a beam-and-traceinterposer;

[0016]FIG. 5 illustrates a side view of a beam-and-trace interposer;

[0017]FIG. 6 illustrates a perspective view of a beam-and-traceinterposer;

[0018]FIG. 7 illustrates a beam-and-trace interposer array comprisingmultiple beam-and-trace interposers coupled together;

[0019]FIG. 8 illustrates an assembly including a die mounted to apackage, which is mounted to a PCB by a beam-and-trace interposer;

[0020]FIG. 9 is a cross-sectional side view of a conductive columninterposer;

[0021]FIG. 10 shows an assembly that includes a die mounted to apackage, which is mounted to a PCB by a conductive column interposer;

[0022]FIG. 11 is a flow diagram illustrating a process for making abeam-and-trace interposer;

[0023]FIG. 12 is a flow diagram illustrating a process for making aconductive column interposer; and

[0024]FIG. 13 is a flow diagram illustrating a process for mounting aninterposer to a device package and a motherboard.

DETAILED DESCRIPTION

[0025] An interposer to couple a microelectronic device package to acircuit board is described. Note that in this description, references to“one embodiment” or “an embodiment” mean that the feature being referredto is included in at least one embodiment of the present invention.Further, separate references to “one embodiment” in this description donot necessarily refer to the same embodiment; however, neither are suchembodiments mutually exclusive, unless so stated and except as will bereadily apparent to those skilled in the art. For example, a feature,structure, act, etc. described in one embodiment may also be included inother embodiments. Thus, the present invention can include a variety ofcombinations and/or integrations of the embodiments described herein.

[0026] As described in greater detail below, the interposer is made froma PCB substrate and is constructed as follows. A PCB substrate(hereinafter “PCB substrate” or simply “substrate”) is coated on its topand bottom surfaces with a conductive material, such as copper. Multiplevia holes are then drilled through the substrate, to form atwo-dimensional array of via holes, and then coated inside with theconductive material to provide an electrically conductive channel fromthe top surface to the bottom surface through each via hole. Theconductive material on the top and bottom surfaces is then selectivelyetched to form multiple traces, each in electrical contact with theconductive coating in one of the via holes. Grooves are then carved inthe substrate between the via holes and traces.

[0027] In one embodiment, the substrate is then cut into strips throughthe middle of each row of via holes, to produce a number of individualbeam-and-trace interposers that can be coupled between a device packageand another PCB (e.g., motherboard). Each individual interposer includesa row of electrically conductive channels, each formed from thehalf-barrel of a via hole. Two or more of these interposers can beaffixed together to form an array that can be coupled as one unitbetween the package and the motherboard.

[0028] In another embodiment, an interposer is constructed in a mannersimilar to the above, except that the substrate is not cut into strips,and each via hole is filled completely with a conductive material. Theconductive material in the via holes forms an array of solid conductivecolumns through the substrate as the electrical contacts between thepackage and motherboard.

[0029] The interposer described herein solves the problem of reducedsolder joint shear strength that results from reduction of solder ballpitch and the associated package standoff reduction. The interposerprovides a stronger solder joint in terms of shear strength by providinga greater standoff distance between the package and PCB thanconventional solder balls provide. The I/O density can be significantlyincreased, because copper traces are used as the electrical conduitinstead of solder balls, and can be made to be much thinner than currentsolder balls since the beam interposer supports them. Thus, theinterposer described herein can significantly increase the I/O densityof a BGA for a device package, without the disadvantages associated withthe current state-of-the-art.

[0030] A process for making a beam-and-trace interposer will now bedescribed in greater detail, with reference to FIGS. 2 through 8 andFIG. 11. Referring first to FIG. 11, at 1101 the top and bottom surfacesof a PCB substrate are coated with a conductive material, such as coppercladding (as henceforth assumed herein). This may be accomplished usingany well-known copper coating process such as commonly used in PCBfabrication. The substrate can be composed of the same material fromwhich PCBs are commonly constructed, such as FR4. In one embodiment, thesubstrate is 1.5 mm (0.062″) thick, providing a greater standoffdistance between the package and the motherboard in comparison to the0.024″ diameter solder balls commonly used to couple a package tomotherboard.

[0031] At 1102, multiple through holes (“via holes”) are drilled in thesubstrate, to form an array of via holes. In one embodiment, the viaholes are 0.245 mm (0.010″) in diameter and are drilled at 0.020″centers. The result is illustrated in FIG. 2, which shows a PCBsubstrate 21 with an array of via holes 22 drilled in it. Next, at 1103a conductive coating, which may also be copper, is formed on the wallsof all of the via holes, such that the coating completely coats theinside of the via holes and contacts the conductive coating on the topand bottom surfaces of the substrate. This procedure creates anelectrical connection from the top side to the bottom side of thesubstrate. At 1105 the copper on the top and bottom surfaces isselectively etched in a photo etching process to form multiple coppertraces (also called “pads”). The result is illustrated in FIG. 3A, whichshows essentially linear copper traces 31, each through a different rowof via holes. Note, however, that different trace patterns may be usedin alternative embodiments. At 1105, a routing or diamond saw process isused to carve linear grooves in the top and bottom surfaces of thesubstrate, between the via holes and traces. In general, it issufficient to carve these grooves all in one direction. The dashed linesin FIG. 3B show where the grooves would be made for the embodiment ofFIG. 3A. The grooves make the substrate more compliant in the event oftemperature coefficient expansion (TCE) rate mismatch between thepackage and the interposer. Next, at 1106 the substrate is cut intoindividual substrate members through the middle of each row of via holesand halfway between each row of via holes, using a diamond saw or othersuitable tool, to produce a number of individual beam-and-traceinterposers. The dashed lines in FIG. 3C show were the cuts would bemade.

[0032] An example of such an interposer is illustrated in FIGS. 4, 5 and6. FIGS. 4 and 5 show two orthogonal views of the interposer 40;specifically, FIG. 4 shows the top or bottom view (these views areidentical) while FIG. 5 shows the corresponding side view. FIG. 6 showsa perspective view of a portion of the interposer 40. Eachbeam-and-trace interposer 40 has multiple, copper-coated half-barrels 41in its side (formed from the bisected via holes in a given row),multiple, roughly semi-circular copper pads 42 on its top and bottomsurfaces, and multiple grooves 43 carved in the top and bottom surfacesof the substrate. The pads 42 and via half-barrels 41 will formelectrically conductive channels between the device package and themotherboard.

[0033] The semi-circular copper pads give the interposer more surfacearea to attach to the package substrate or the motherboard, resulting ina stronger solder joint. The copper pads and barrels can be plated withgold, silver or solder to protect the copper coating from oxidizing andto provide a wettable surface area for the solder joint. The grooves inthe beam give the beam a horizontal axis that complies with the thermalco-efficient of expansion (TCE) mismatch between the component substrateand motherboard warp.

[0034] Finally, at 1107 two or more of these beam-and-trace interposersare affixed together, using glue (e.g., epoxy) or any other suitablefastening substance or structure, to form an interposer comprising anarray of these individual beam-and-trace interposers, to be coupled as aunit between the device package and the motherboard. FIG. 7 shows anexample of an interposer comprising multiple individual beam-and-traceinterposers 40 attached together in this manner to form a singleinterposer 71. In other embodiments, multiple beam-and-trace interposerscan be individually coupled between the package and the motherboard. Instill other embodiments, it is possible that only a singlebeam-and-trace interposer (i.e., only one beam) may be required.

[0035]FIG. 8 illustrates how the beam-and-trace interposer 71 can beused to couple a microelectronic device package to a PCB. A die 82 ismounted to the device package 81, which is coupled to one side of abeam-and-trace interposer 71. The opposite side of the interposer 71 iscoupled to a PCB 84 to make the electrical and mechanical connectionnecessary for the device to function. FIG. 13 illustrates a normal SMTsolder paste and reflow process that can be used to attach abeam-and-trace interposer to a device package and a PCB. At 1301 asolder paste of 0.178 mm (0.007″) thickness is printed on the traces ofthe top surface of the interposer using a stencil screen printer. At1302 the copper pads on interposer are lined up with correspondingcontacts of the package (to which the die has previously been mounted),and the interposer is then placed onto the package. The two assembliesare then reflowed in a solder reflow oven to make electrical andmechanical connections between the pads of the interposer and thecontacts of the package. At 1304 a standard process is used to mount thebottom side of the interposer to the PCB.

[0036] Assuming the interposer is formed from a standard-thickness PCBsubstrate, the resulting standoff distance between the package and themotherboard is approximately six times taller than when standard solderballs are used to couple the package to the motherboard. The interposergreatly improves the shear strength of the solder joints. The tallersolder joint allows less movement of the solder joint between the beamand trace interposer and the component substrate/mother board duringthermal cycling.

[0037] The beam-and-trace interposer provides the vertical support forthe traces that connect the package to the motherboard. This techniqueallows the traces to be very thin but does not adversely affect thevertical strength of the interposer. This technique thereby allows theinterposer to handle heavy heat sinks with preloads without theinterposer collapsing.

[0038]FIGS. 9, 10 and 12 relate to another embodiment of a PCB-basedinterposer, referred to as a conductive column interposer. Thisembodiment can be constructed in a manner similar to the beam-and-traceinterposer, except that the substrate is not cut into multiple beams,and each via hole is filled completely with a conductive material. Theconductive material forms an array of solid conductive columns throughthe substrate to provide the electrical contacts between the package andmotherboard.

[0039]FIG. 9 shows a side cross-sectional view of a conductive columninterposer according to one embodiment. As can be seen, the interposer90 includes solid conductive columns 91 within the via holes as well asgrooves 92 in the substrate between the via holes. As shown by thedashed lines in FIG. 3D, however, the grooves 92 are made along twoperpendicular axes in the conductive column interposer, rather thanalong just one axis as in the beam-and-trace interposer. FIG. 10 showsan assembly that includes the conductive column interposer 90 coupled toa device package 102 (on which a die 103 is mounted) and a PCB 104.

[0040]FIG. 12 shows a process for making a conductive column interposer.In the illustrated process, blocks 1201 through 1204 are essentiallyidentical to blocks 1101 through 1104 described above, respectively, andtherefore will not be discussed again in detail. Following block 1204,at block 1205 the via holes are filled with a high-lead-contentconductive material, leaving a small layer of the material over thecopper traces on the top and bottom surface of the substrate. The resultis in an array of solid conductive columns through the via holes. Thefill material may be, for example, high-temperature solder deposited bya hot air solder leveling (HASL) process or over-plating process. Ahigh-lead-content material is used so that the conductive columns have ahigh melting temperature, to prevent them from reflowing when theinterposer is subsequently mounted to the motherboard. The compositionof the conductive columns may be, for example, 85 percent lead (Pb) and15 percent tin (Sn). Note, however, that other conductive materials,such as silver or copper, can be used to fill the via holes if the useof lead is considered undesirable (e.g., for environmental reasons).

[0041] At 1206, linear grooves are carved in the top and bottom surfacesof the substrate between the via holes and traces in essentially thesame manner as described for block 1105, above, except that grooves arecarved both horizontally and vertically.

[0042] The conductive column interposer may be coupled to a devicepackage and motherboard using essentially the same process as used forthe beam-and-trace interposer, as described in conjunction with FIG. 13.

[0043] Thus, an interposer to couple a microelectronic device package toa circuit board has been described. Although the present invention hasbeen described with reference to specific exemplary embodiments, it willbe evident that various modifications and changes may be made to theseembodiments without departing from the broader spirit and scope of theinvention as set forth in the claims. Accordingly, the specification anddrawings are to be regarded in an illustrative sense rather than arestrictive sense.

What is claimed is:
 1. A method comprising: creating a plurality of rowsof via holes through a circuit board substrate from a first surface ofthe substrate to a second surface of the substrate; forming a conductivelayer on the first surface and on the second surface; forming aconductive path through each of the via holes from the first surface tothe second surface; and severing the substrate through each row of viaholes and between each row of via holes along a coordinate axis, toproduce a plurality of elongate substrate members.
 2. A method asrecited in claim 1, further comprising coupling at least one of theelongate substrate members between an electronic component package and acircuit board.
 3. A method as recited in claim 1, further comprisingaffixing two or more of the elongate substrate members together to forman interposer.
 4. A method as recited in claim 3, wherein said affixingcomprises affixing two or more of the elongate substrate memberstogether to form an interposer configured with an array of via holes. 5.A method as recited in claim 4, further comprising coupling theinterposer between an electronic component package and a circuit board.6. A method as recited in claim 1, further comprising forming aplurality of elongate grooves in the first surface and in the secondsurface of the substrate, prior to said severing.
 7. A method as recitedin claim 1, wherein said grooves are formed parallel to each otherbetween rows of via holes.
 8. A method of manufacturing an interposer,the method comprising: creating a plurality of rows of via holes througha circuit board substrate from a first surface of the substrate to asecond surface of the substrate, the first surface and the secondsurface being coated with a conductive material; forming a conductivelayer in each of the via holes to provide a conduction path through eachof the via holes from the conductive material on the first surface tothe conductive material on the second surface; selectively removing someof the conductive material from the first surface and the second surfaceto form a plurality of traces on the first surface and the secondsurface, each trace in electrical contact with the conductive layer inat least one of the via holes; and severing the substrate to produce aplurality of individual substrate members, by cutting the substratethrough the middle of the via holes in each row of via holes and betweeneach row of via holes along a particular axis.
 9. A method as recited inclaim 8, further comprising affixing two or more of the plurality ofindividual substrate members together to form an interposer as asubstantially planar array.
 10. A method as recited in claim 9, furthercomprising coupling the interposer between an electronic componentpackage and a circuit board.
 11. A method as recited in claim 10,wherein the electronic component package includes a semiconductor die,and wherein the circuit board is a motherboard.
 12. A method as recitedin claim 8, further comprising forming grooves in the first surface andthe second surface of the substrate between the via holes.
 13. A methodas recited in claim 8, wherein the conductive coating is a surface layerapplied in each of the via holes.
 14. A method as recited in claim 8,further comprising coupling at least one of the individual substratemembers between an electronic component package and a circuit board. 15.A method of manufacturing an interposer, the method comprising: creatinga plurality of via holes through a circuit board substrate from a firstsurface of the substrate to a second surface of the substrate; andcreating a solid conductive column through each of the via holes, theconductive column forming an electrical path from the first surface tothe second surface.
 16. A method as recited in claim 15, furthercomprising coating the first surface and the second surface with aconductive material.
 17. A method as recited in claim 16, furthercomprising selectively removing some of the conductive material from thefirst surface and the second surface to form a plurality of traces onthe first surface and the second surface, each trace in electricalcontact with the conductive column of one of the via holes.
 18. A methodas recited in claim 15, further comprising forming grooves in the firstsurface and the second surface of the substrate between the via holes.19. A method as recited in claim 15, further comprising coupling theinterposer between an electronic component package and a circuit board.20. A method as recited in claim 19, wherein the electronic componentpackage includes a semiconductor die and the circuit board is amotherboard.
 21. A method as recited in claim 15, wherein each of theconductive columns has a composition of tin (Sn) and lead (Pb).
 22. Amethod as recited in claim 21, wherein the composition comprises atleast 81% lead (Pb).
 23. A method of manufacturing an interposer, themethod comprising: creating a plurality of via holes through a circuitboard substrate from a first surface of the substrate to a secondsurface of the substrate; creating a conductive path through each of thevia holes from the first surface to the second surface; and forming aplurality grooves in the first surface and the second surface of thesubstrate between the via holes.
 24. A method as recited in claim 23,wherein said forming a plurality grooves comprises: forming a firstplurality of grooves in the first surface of the substrate; forming asecond plurality of grooves in the first surface of the substrate,perpendicular to the first plurality of grooves; forming a thirdplurality of grooves in the second surface of the substrate; forming afourth plurality of grooves in the second surface of the substrate,perpendicular to the third plurality of grooves.
 25. A method as recitedin claim 23, further comprising selectively removing some of theconductive material from the first surface and the second surface toform a plurality of traces on the first surface and the second surface,each trace in electrical contact with the conductive column of one ofthe via holes.
 26. A method as recited in claim 23, wherein saidcreating a conductive path through each of the via holes comprisesforming a thin conductive layer on a surface of each of the via holes.27. A method as recited in claim 26, further comprising severing thesubstrate to produce a plurality of elongate beams, by cutting thesubstrate through the middle of the via holes in each row of via holesand between each row of via holes along a particular axis.
 28. A methodas recited in claim 27, further comprising affixing two or more of theplurality of beams together in an array configuration to form theinterposer.
 29. A method as recited in claim 23, wherein said creating aconductive path through each of the via holes comprises forming a solidconductive column through each of the via holes.
 30. A method as recitedin claim 23, wherein each of the conductive columns has a composition oftin (Sn) and lead (Pb).
 31. A method as recited in claim 30, wherein thecomposition comprises at least 81% lead (Pb).
 32. A method as recited inclaim 23, further comprising coupling the interposer between anelectronic component package and a circuit board.